It is common in the art to combine bipolar transistors and complementary metal-oxide silicon ("CMOS") field effect transistors in a bipolar-complementary metal-oxide-silicon ("BiCMOS") transistor configuration. BiCMOS configurations are widely used in fabricating ever smaller, faster and increasingly complex integrated circuits. BiCMOS integrated circuits are fabricated layer-by-layer, typically on a silicon substrate, with one or more layers at least partially covered with an oxide such as SiO.sub.2.
However in BiCMOS fabrication, some process steps used to fabricate high performance bipolar devices frequently cannot be used to simultaneously create MOS devices. The inability to make dual use of many processing steps thus adds to the complexity of BiCMOS fabrication, and can result in reduced device yield.
In general, high cut-off frequency performance is desired in a BiCMOS circuit. Such high frequency performance is enhanced by providing small geometry bipolar devices having reduced junction capacitance and extrinsic base resistance, obtained by using increased extrinsic base region dopant concentration. Small geometry devices not only promote switching speed, but also allow greater device density within a BiCMOS circuit. But fabricating smaller geometry devices can require tighter fabrication process alignment tolerances that increase manufacturing complexity.
Scaling-down bipolar devices can promote degradation of device characteristics, especially current gain and off-state leakage. Degradation occurs because scaled-down dimensions and increased doping concentrations tend to increase the electric field intensities to which the devices are exposed, since the operating voltage level is generally fixed. For example, reverse biased depletion regions within a small geometry bipolar transistor can be subjected to relatively high intensity electric fields.
Electrons encountering these increased field intensities acquire increased kinetic energy and accelerate beyond an equilibrium state, becoming what is commonly termed "hot electrons" or "hot carriers". Hot carriers can escape from the semiconductor, surmount and remain trapped within an oxide layer within the device. The trapped charges form a local depletion region, wherein holes and electrons recombine, typically with a decreased surface recombination lifetime. Unfortunately, the holes required to neutralize or satisfy the surface recombination are holes diverted from the transistor's base current. The resultant surface effect increases base current, thereby decreasing the transistor current gain (.beta.).
It is known in the art to obtain a higher current gain (.beta.) device by providing an abrupt emitter-base transition, with resultant improved emitter injection efficiency. However, fabricating such emitter-base regions in small geometry bipolar devices using BiCMOS compatible techniques is challenging. This is because of the difficulty in independently controlling the junction depths and dopant profiles of the various doped regions.
It is known in the art to improve bipolar device high frequency performance by increasing dopant concentrations in the extrinsic base region, thereby reducing extrinsic base resistance. But under reverse bias conditions, the increased dopant concentrations result in smaller depletion regions that increase the electric field to which the emitter-base junction is subjected. This in turn can produce increased numbers of hot carriers, with resultant reduced breakdown voltage and degradation of device performance.
It is also known in the art to suppress hot carrier effects using a laterally graded emitter structure that decreases peak electric fields between the emitter and base regions of a transistor. See for example H. Honda, et al., I.E.E.E. CH2865-4/90/0000-0227 (1990). But while it is recognized that an abrupt emitter-base transition can improve bipolar current gain (.beta.), the method disclosed by Honda, et al. does not readily allow independent control over the bipolar transistor active (intrinsic) and inactive (extrinsic) base regions, or the profile of the laterally graded emitter for purposes of optimizing bipolar performance. Further, the method disclosed by Honda, et al. does not yield small geometry, self-aligning devices, or the improved high frequency performance that such small geometry can provide. In short, while contemporary integrated circuit design demands small geometry high speed bipolar transistors, the smaller geometry dictates stricter manufacturing process alignments. Further, smaller geometry can promote significant hot carrier effects that degrade bipolar transistor performance. While reducing extrinsic base resistance can enhance bipolar transistor performance, the resultant increased extrinsic base region dopant concentration promotes hot carrier generation.
What is needed is a process to fabricate a small geometry, self-aligned bipolar transistor having a laterally graded emitter to suppress hot carrier generation. Such bipolar transistor should exhibit decreased extrinsic base resistance, and improved emitter-base junction breakdown voltage characteristics. Preferably such process and structure should be BiCMOS compatible, allowing bipolar and CMOS fabrication steps to occur simultaneously on a common integrated circuit substrate. The present invention discloses such a process and structure.